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PI2EQX3202
3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis
Features
* * * * * * * * * Supports data rates up to 3.2Gbps on each lane Adjustable Transmiter De-Emphasis & Amplitude Adjustable Receiver Equalization Two Spread Spectrum Reference Clock Buffer Outputs 100 Differential CML I/O's Low Power (100mW per Channel) Standby Mode - Power Down State VCC Operating Range: 1.8V +/-0.1V Packaging (Pb-free & Green): - 84-ball LFBGA
Description
Pericom Semiconductor's PI2EQX3202 is a low power, signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX3202 supports four 100 Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the re-driver. In addition to providing signal re-conditioning, Pericom's PI2EQX3202 also provides power management Stand-by mode operated by a Bus Enable pin.
Block Diagram

Pin Description

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PS8819
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis Pin Description
Pin # B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 C3 D3 E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 C8 D8 G3 H3 G8 H8 A3, B4, B5 A4, C4, C5 G2, J2, J4 H2, K2, J5 B6, A5 C6, A6 K3, K4 J6, J9 B7, A7 C7, A8 K9, G9 K10, H9 C10 D10 C1 D1 G10 H10 G1 H1 Pin Name VDD AI+ AIGND BI+ BICI+ CIDI+ DISEL[0:2]_A SEL[0:2]_B SEL[0:2]_C SEL[0:2]_D SEL[3:4]_A SEL[3:4]_B SEL[3:4]_C SEL[3:4]_D SEL[5:6]_A SEL[5:6]_B SEL[5:6]_C SEL[5:6]_D AO+ AOBO+ BOCO+ CODO+ DOI/O PWR I I PWR I I I I I I I I I I I I I I I I I I O O O O O O O O 1.8V Supply Voltage Positive CML Input Channel A with internal 50 pull down Negative CML Input Channel A with internal 50 pull down Supply Ground Positive CML Input Channel B with internal 50 pull down Negative CML Input Channel B with internal 50 pull down Positive CML Input Channel C with internal 50 pull down Negative CML Input Channel C with internal 50 pull down Positive CML Input Channel D with internal 50 pull down Negative CML Input Channel D with internal 50 pull down Selection pins for equalizer (see Amplifier Configuration Table) w/ 50K internal pull up Description
Selection pins for amplifier (see Amplifier Configuration Table) w/ 50K internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50K internal pull up Positive CML Output Channel A internal 50 pull up during normal operation and 2K pull up otherwise. Negative CML Output Channel A with internal 50 pull up during normal operation and 2K pull up otherwise. Positive CML Output Channel B with internal 50 pull up during normal operation and 2K pull up otherwise. Negative CMLOutput Channel B with internal 50 pull up during normal operation and 2K pull up otherwise. Positive CMLOutput Channel C with internal 50 pull up during normal operation and 2K pull up otherwise. Negative CMLOutput Channel C with internal 50 pull up during normal operation and 2K pull up otherwise. Positive CMLOutput Channel D with internal 50 pull up during normal operation and 2K pull up otherwise. Negative CMLOutput Channel D with internal 50 pull up during normal operation and 2K pull up otherwise.
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis Pin Description (Continued)
Pin # A9, A10, B9, C9 H6 H5 K5, K6 K7, K8 J7 K1 A1, A2, B2, C2 Pin Name EN_ [A,B,C,D] CKINCKIN+ OUT0+, OUT0OUT1+, OUT1IREF EN_CLK NC I/O I I I O Differential Reference Clock Output O O I N/A External 475 resistor connection to set the differential output current Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTxoutputs. When LOW, it disables these outputs, to HI-z state. These outputs will be pulled down by external 50 termination resistor in application circuit. No connect pins. For normal operation, leave pins floating Description Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output. When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- outputs will be pulled up to VDD by internal 2k resistor. Differential Input Reference Clock
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage.......................................................... -0.5V to VCC +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature.............................................................. 0 to +70C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Output Swing Control
SEL3_[A:D] 0 0 1 1 SEL4_[A:D] 0 1 0 1 Swing 1x 0.8x 1.2x 1.4x
Output De-emphasis Adjustment
SEL5_[A:D] 0 0 1 1 SEL6_[A:D] 0 1 0 1 De-emphasis 0dB -2.5dB -3.5dB -4.5dB
Equalizer Selection
SEL0_[A:D] 0 0 0 0 1 1 1 1 SEL1_[A:D] 0 0 1 1 0 0 1 1 SEL2_[A:D] 0 1 0 1 0 1 0 1 Compliance Channel No Equalization [0:1.5dB] @ 1.25 GHz [0:2.5dB] @ 1.25 GHz [0:3.5dB] @ 1.25 GHz [0:4.5dB] @ 1.25 GHz [0:5.5dB] @ 1.25 GHz [0:6.5dB] @ 1.25 GHz [0:7.5dB] @ 1.25 GHz
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis AC/DC Electrical Characteristics for 2.5 Gbps Quad Repeater/Equalizer (VDD = 1.8 0.1V)
Symbol Ps Parameter Supply Power Latency CML Receiver Input RLRX Return Loss Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage DC Differential Input ZRX-DIFF-DC Impedance ZRX-DC DC Input Impedance Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) Total Jitter Deterministic jitter 1.5 0.3 0.2 Ulp-p psrms Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. Max. 0.1 0.6 Units W ns
2.0
50 MHz to 1.25 GHz 0.175
12 1.200 150 80 40 100 50 120 60
dB V mV
Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1.

Figure 1. Test Condition Referenced in the Electrical Characteristic Table
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis AC/DC Electrical Characteristics for 2.5 Gbps x2 Lane Repeater/Equalizer (TA = 0 to 70C)
Symbol Parameter Conditions Differential Swing | VTX-D+ - VTX-D- | | VTX-D+ + VTX-D- | / 2 20% to 80% (1) Single ended 40 80 75 VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | 0.8 50 100 Min. Typ. Max. Units CML Transmitter Output (100 differential) VDIFFP VTX-C tF, tR ZOUT ZTX-DIFF-DC CTX VTX-DIFFP-P Output Voltage Swing Common-Mode Voltage Transition Time Output resistance DC Differential TX Impedance AC Coupling Capacitor Differential Peak-to-peak Ouput Voltage 400 VCC0.3 150 60 120 200 1.8 ps nF V 900 mVp-p
LVCMOS Control Pins VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current 0.65 x VDD VDD 0.35 x VDD 250 500 V
A
Note: 1. Using K28.7 (0011111000) pattern)
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis AC Switching Characteristics for Clock Buffer (VDD = 1.8 0.1V, AVDD = 1.8 0.1V) (3)
Symbol Trise / Tfall Trise / Tfall VHIGH VLOW VCROSS VCROSS TDC Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time Variation Voltage High including overshoot Voltage Low including undershoot Absolute crossing point voltages Total Variation of Vcross over all edges Duty Cycle (input duty cycle = 50%)
(2) (1)
Min 125
Max. 525 75
Units ps
Notes 1 1 1 1 1 1 2
660 -150 -200 200 45
900 550 250 55 % mV
Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2, Rp = 49.9, and 2pF.
Configuration Test Load Board Termination
Rs 33 5% CLKBUF
Clock TLA Clock# TLB
Rs 33 5% 2pF 5%
475 1%
Rp 49.9 1%
Rp 49.9 1%
2pF 5%
Note: * TLA and TLB are 3" transmission lines.
Figure 2. Configuration test load board termination
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PI2EQX3202 3.2Gbps, 4 Differential Channel, Serial Re-driver with Built-in Equalization & De-emphasis Packaging Mechanical: 84-Ball LFBGA (NB)
0.80 BSC
7.20 BSC.
0.40 BSC.
0.40 BSC. 7.20 BSC.
0.50 0.05
Ordering Information
Ordering Number PI2EQX3202NB PI2EQX3202NBE Package Code NB NBE Package Description 84-lead LFBGA Pb-free & Green 84-Ball LFBGA
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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